PATMANATHAN, G.; OOI, C. Y.; ISMAIL, N. .; AID, S. THERMAL-AWARE TEST SCHEDULING AND FLOOR PLANNING FOR THREE-DIMENSIONAL STACKED INTEGRATED CIRCUITS. Journal of Engineering and Technology (JET), [S. l.], v. 15, n. 2, p. 203–218, 2024. DOI: 10.54554/jet.2024.15.02.013. Disponível em: https://jet.utem.edu.my/jet/article/view/6565. Acesso em: 6 apr. 2025.