PATMANATHAN, G.; OOI, C. Y.; ISMAIL, N. .; AID, S. THERMAL-AWARE TEST SCHEDULING AND FLOOR PLANNING FOR THREE-DIMENSIONAL STACKED INTEGRATED CIRCUITS. Journal of Engineering and Technology (JET), [S. l.], v. 15, n. 2, 2024. Disponível em: https://jet.utem.edu.my/jet/article/view/6565. Acesso em: 4 jan. 2025.