Optimization of Gate Recess Step and Elimination of the Dome Effect for Highly Reliable and Reproducible Novel pHEMT Device

Abstract

We report a comprehensive etching study on the gate recess-processing step in novel pseudomorphic High Electron Mobility Transistor (pHEMT) fabrication. The experiments focused on the etchant composition and elimination of the cap layer residue (Dome Effect) at the etching trenches. The optimised processing flow using highly selective Succinic Acid is aimed for moderate cap layer etching, with an etching rate of 240 Å/min and InGaAs-InAlAs selectivity of 140. The percentage of the Dome height to etching depth is 30%, consistent throughout the etching surface, however, can be further improved by controlling the etching time to the etch-stop layer. The optimised processing steps will enhance the device’s robustness, especially in the complete processing steps for Monolithic Microwave Integrated Circuit (MMIC) fabrication, tailored for high-gain and low noise in satellite communication applications.